In the manufacture of printed circuits, it is commonplace to provide planar boards having circuitry on each side thereof. It is also commonplace to produce boards comprised of integral planar laminates of insulating substrate and conductive metal, wherein one or more parallel innerlayers or planes of the conductive metal, separated by insulating substrate, are present within the structure with the exposed outer surfaces, along with the innerlayers, of the laminate containing printed circuit patterns.
The typical manufacturing sequence for producing printed circuit boards begins with a copper-clad laminate. The copper-clad laminate typically comprises a glass reinforced epoxy insulating substrate with copper foil adhered to both planar surfaces of the substrate. Other types of insulating substrates, including paper phenolic and polyimides, may also be used. In the case of multi-layer boards, the starting material is a copper clad laminate, which comprises innerlayers of circuitry.
Simple printed circuit boards and innerlayers of multi-layered circuit boards are generally produced through a technique called print and etch. In this manner, a photopolymer is laminated or coated on the copper surface of a copper clad laminate. The photopolymer is then selectively imaged using negative or positive photomask technology and developed to produce the desired circuit pattern on the surfaces of the copper clad laminate. The exposed copper is then etched away and the photopolymer stripped, revealing the desired circuit pattern.
Embedded passive technology (EPT) is a relatively new technology that has been used to fabricate passives, such as resistors and capacitors, into printed circuit boards during the board fabrication process. Compared with integrated passives, in which passive arrays and networks are arranged on carrier substrates, embedded passives are fabricated into the substrate during processing. EPT is driven by various factors, including the need for better electrical performance, higher packaging density of passives, and potential cost savings. Using EPT, passives may be placed directly below the active device, thus resulting in a shorter distance between the passive and active components and reducing the parasitic effect associated with surface mounted passives, resulting in better signal transmission and less cross talk.
One EPT process is described in U.S. Pat. No. 6,281,090 to Kukanskis et al., the subject matter of which is incorporated herein by reference in its entirety. This process involves the following sequence of processing steps: 1) applying an etch resist on the surface of a metal clad laminate (or multilayer package) in a desired pattern, wherein the pattern preferably defines the conductive circuits desired in a positive manner and defines the areas between the circuits and locations for the resistors in a negative manner; 2) etching away the exposed copper and preferably removing the etch resist; 3) activating the surfaces to accept plating thereon; 4) applying a plating mask which covers substantially all of the surfaces except for the areas where the resistors are to be plated; 5) plating the exposed areas with a resistive material; 6) stripping away the plating mask; and 7) coating the surface of the board with a protective coating.
A similar EPT process is described in U.S. Pat. No. 6,767,445 to Kukanskis et al., the subject matter of which is herein incorporated by reference in its entirety, but does not use a mask during the plating step. Instead, this process selectively activates the surface of the metal-clad laminate so as to prevent the entire surface of the substrate from being activated. The selective activation ste
is generally accomplished using a mask to prevent the entire substrate from being activated. The remaining steps in the process are the same or similar to the process steps described in U.S. Pat. No. 6,281,090.
A preferred resistive metal for use in the process of the invention is an electroless nickel-phosphorus solution. Resistance values that can be obtained using prior art electroless nickel-phosphorus compositions generally range only from 10 to 100 ohms/square. However, embedded resistors having resistance values between about 10 to 10,000 ohms/square±5% are highly desirable.
Furthermore, in order to embed the layer, it is manufactured as part of a sandwich of layers that are pressed together in a press cycle at a temperature of between about 140 and 200° C. and a pressure between about 150 and 200 psi. After the press cycle, a change in resistance values of up to 3 percent is generally observed.
It would be highly desirable to expand the resistance range of the nickel phosphorus resistor material while maintaining the stability of the resistance during the press cycle. To that end, the present inventors have determined that the codeposition of another material with the electroless nickel-phosphorus composition can expand the resistance range of the plated resistor. The codeposited material is generally selected from various particles that remain stable under the press conditions described above.